The present invention relates to an arbitration circuit for arbitration, in using a shared circuit such as a memory, between functional blocks in a circuit such as a digital circuit in which the shared circuit is used exclusively by one of the functional blocks at a time.
Digital circuits that process various data often use memories so as to temporally store data. If a large number of circuits requiring memories (hereinafter, referred to as functional blocks) are provided, the memories are prepared for the respective functional blocks in some cases. However, to implement the same capacity, in both cases of implementation in LSI and on a board, provision of a smaller number of large-capacity memories is more advantageous than provision of a large number of small-capacity memories in terms of, for example, cost, implementation area and the number of mounting steps. In view of this, a minimum number of memories corresponding to the total capacity necessary for the functional blocks are generally provided to be shared among the functional blocks.
However, only a small number (one or two) of inputs/outputs are generally provided to read/write (hereinafter, collectively referred to as access) data stored in memories. To access different data sets in the memories from functional blocks at respective timings independently, operation of permitting access to the memories without contradiction and interruption by adjusting requests for access from the functional blocks is needed. Hereinafter, this operation will be referred to as arbitration. A circuit for implementing the arbitration will be hereinafter referred to as an arbitration circuit.
In recent years, semiconductors have been advanced remarkably, and the speed of internal circuits has increased to the order of several hundreds of MHz to several hundreds of GHz. In addition, the semiconductors come to be used in system LSI (i.e., are integrated), so that a memory is shared among a larger number of circuits. The amount of data has also rapidly increased accordingly.
On the other hand, memories have also been advanced, but the operation frequencies thereof are still in the range of 200 to 400 MHz. That is, the memories have not been advanced as rapidly as semiconductors. A large number of semiconductors include function cores which require memories, so that the memories and their peripheral components tend to degrade the performance of a system. Therefore, effective use of memories is necessary to enhance the performance of the system, and an arbitration circuit such as the above-described digital circuit plays an importance role.
To estimate the performance of a memory, two points of views are considered. One is the bandwidth and the other is the latency. The former is the upper limit of the average amount of data in access in normal operation. In theory, this upper limit is determined by the data width in a memory, the clock frequency and overhead of memory access. The total access amount necessary for the functional blocks needs to be determined not to exceed the bandwidth. The latter is the time during which when a plurality of access requests are issued at the same time, an unselected request is kept waiting before being actually accepted. The latency occurs when the amount of data used in access is smaller than the bandwidth in average but a plurality of access requests are issued at a time with low-priority access requests kept waiting. In a system performing real-time processing, the latency might cause serious troubles, and thus careful consideration is needed to prevent the latency from causing serious troubles.
In view of this, an arbitration circuit satisfying the foregoing requirements is needed. For arbitration, allocation of priority levels and a round-robin scheme are generally adopted. The priority levels are used to indicate which access request is to take precedence when a plurality of access requests are issued at the same time. These access requests are accepted in order of descending priority. However, if the processing is always performed in this manner, access requests with relatively low priority levels might be left unexecuted for a long time. Therefore, a scheme with which if an access request, even a high-priority access request, is once accepted, the priority level thereof is temporally lowered based on a criterion so that a lower-priority access request is accepted during a given period of time, is often adopted. This scheme is called a round-robin scheme.
In this way, in a conventional technique (e.g., Japanese Unexamined Patent Publication No. 1-124051), when a plurality of access requests are issued at the same time, arbitration is performed in accordance with priority levels based on a history of accepted accesses.
Functional blocks configured to use a shared memory generally operate independently of each other, so that access requests to the shared memory from these functional blocks might coincide with each other. Even if this possibility of the coincidence is extremely low, failure of the system should be prevented as long as the possibility exists.
In the above-mentioned conventional technique, access requests are issued with no advance notice, and thus an arbitration circuit needs to perform arbitration at every issue. If an access request which does not have such a high priority level but is for access in a long period is issued and, immediately after the request is accepted, a high-priority request is issued, the request immediately before the acceptance is forced to be canceled or interrupted, or subsequent high-priority requests are forced to be kept waiting, for example. The former might cause overhead or degradation in performance, and the latter might cause failure of a system.
To avoid these problems by using the conventional technique, cancellation or latency is estimated with a margin and a circuit for the margin is additionally prepared. This increases costs for LSI and memories.